1. Field of the Invention
The invention relates to the design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for simulating topography of a conductive material in a semiconductor wafer after Copper deposition and prior to polishing.
2. Related Art
Electroplating (ECP) and chemical mechanical planarization (CMP) processes have gained broad applications in copper (Cu) interconnect pattern generation in the back end process of sub-130 nm technology nodes. See, S. Wolf, Silicon Processing for VLSI Era, Vol. 4: Deep Submicron Process Technology, Lattice Press, Sunset Beach, Calif., USA, 2002. Cu is patterned using a process known as damascene process. During the Cu damascene process, trenches and holes are first etched in the oxide material. An ECP process is applied to deposit the Cu onto the whole wafer filling up the trenches. It is followed by a CMP process in which excess overflowing Cu is removed from the oxide surface leaving Cu in the intended trenches and holes; forming interconnect wires and vias. Depending on whether vias and wires are patterned separately or simultaneously, the Cu patterning process is called single damascene process or double damascene process. See FIG. 1.
The Cu and oxide thickness after the damascene process is not uniform across the whole chip. Instead, systematic Cu and oxide thickness variations are observed. These systematic variations are found to be layout dependent. For example, when Cu wire width is changed from 0.9 μm to 100 μm, a >100 nm variation in the Cu thickness is observed. See Z. Stavreva, D. Zeidler, M. Plotner, G. Grasshoff and K. Drescher, “Chemical-mechanical polishing of copper for interconnect formation,” Microelectronic Engineering, Vol. 33, pp. 249-257, 1997. This thickness variation is around 20% for the nominal wire thickness of 550 nm. As feature size scales down, these systematic variations are gaining more significance.
The inventors of the current patent application believe that modeling of the post-CMP Cu and oxide thickness variation in the deep submicron era is critical for the following three reasons. First is the stringent depth of focus (DOF) requirements of the lithography process. With the lithography wavelength stuck at 193 nm and not keeping up with technology scaling, the DOF budget of the lithography tools has been reduced to several hundred nanometers (200˜400 nm). This stringent DOF requirement dictates that the CMP process generates a surface with thickness variation less than 100 nm. Thus it is crucial that one be able to predict oxide and metal thickness variation after CMP with topography modeling and simulation. Second is the need to compare and evaluate the impact of different yield improvement methods. For example, in order to evaluate and compare the topography uniformity improvements resulting from different dummy-fill patterns, a topography model is needed to simulate the resulting thickness variation of each pattern. Third is the need to analyze the impact of the post-CMP thickness variations on timing. Cu and oxide thickness variations result in wire resistance and capacitance variations; which in turn impact the timing of a path in a chip. L. He, A. B. Kahng, K. Tam and J. xiong, “Design of IC interconnects with accurate modeling of CMP,” International Society for Optical Engineering (SPIE) Symposium on Microlithograhpy, March, 2005; see also V. Mehrotra, “Modeling the effects of systematic process variation on circuit performance,” Ph. D. Dissertation, Dept. of EECS, MIT, Cambridge, Mass., USA, 2001.
Topography modeling can help the designer in evaluating interconnect parasitic variations. To model the post-CMP Cu and oxide thickness variations accurately, a model to predict the post-ECP topography is first needed. The post-ECP topography strongly depends on layout patterns, as shown in FIG. 2A. One of the first ECP models to show this dependency is the one proposed by Park. See T. H. Park, “Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits,” Ph.D. Dissertation, Dept. of EECS, MIT, Cambridge, Mass., USA, 2002. In Park's model, the two variables that represent the topography: array height H and step height S, are modeled by two separate polynomials that are independent of each other. The two variables H and S are shown in FIG. 2A. The two polynomials are extracted and calibrated with measured data from test structures. Park's model uses the following formulae for a repeating line/space structure of the type shown in FIG. 2B:H1=aA(LW)+bA(LW)−1+cA(LW)−2+dA(LS)+eA(LW·LS)+ConstAS=aS(LW)+bS(LW)−1+cS(LW)2+dS(LS)+eS(LW·LS)+ConstSwherein H1 is the copper thickness over oxide, and S is step height, and LW is width of a copper wire and LS is spacing between two adjacent copper wires.
The current inventors note that there are several potential problems with Park's model. First, due to failure to consider the physics involved in the ECP process, Park's model does not capture any physical interaction between H1 and S. Therefore, two separate polynomials (as shown above) are used by Park to model these variables. Moreover, Park's model requires use of ten calibration parameters, five for the H1 and five for the step height S (respectively labeled a-e in the above equations). The lack of physical insight into the calibration parameters in Park's model potentially leads to over-fitting.
Second, the empirical model for topography is formulated by Park's model as a function of wire width LW and spacing LS. Current inventors further note that Park's model is sufficient for regular layout patterns in test structures because the values for wire width and spacing are usually the same. However, for practical designs, in any given layout region, various features in various objects are likely to have different widths and spacings. Therefore, using a single set of width and spacing values to represent an entire layout in a window greatly degrades the accuracy of Park's model. Third, in Park's model, the impact of layout patterns on topography is quite local. However, current inventors note that an interaction distance of 20˜50 μm has been observed from experiments. See, for example, M. X. Yang, D. Mao, C. Yu, J. Dukovic and M. Xi, “Sub-100 nm interconnects using multistep plating,” Solid State Technology, Oct., 2003. Hence, Park's calculation of topography based on the wire width and spacing at a feature's location may not be accurate in the first place.
FIG. 3 shows a simplified drawing of a copper electroplating system of the type being modeled by Park. A wafer coated with a thin electrically conductive layer of seed Cu is immersed in chemical solutions containing Cu ions. An external power source is then connected between the seed Cu on the wafer surface and the solid Cu, which act as a cathode and an anode respectively. The Cu ions in the solutions react with the electrons to form Cu on the wafer where the current is passed through. This can be described by the following equation: Cu2++2e−=Cu. The copper ions depleted from the chemical solution will be replenished from the solid copper anode.
A major challenge for the conventional ECP process in the sub-micron era is to fill up the high-aspect-ratio sub-micron trenches with no voids. A void is defined as a hole inside a Cu or a filling material. Presence of a void may cause an open circuit. The primary reason for void formation is a faster deposition rate at the neck of the trench than at its bottom. Therefore, void formation may be avoided by appropriately adjusting the local deposition rate. The current state of art copper electroplating process to prevent void formation is a bottom-up fill process where the deposition starts at the bottom of the trench and move upwards. To achieve such a bottom fill behavior, additive chemicals known as accelerators, suppressors, and levels are typically added to the plating solution. They are adsorbed on the wafer surface to either accelerate or suppress the local deposition rates.
Park does not model the role and interactions of accelerators, suppressors and levels in the bottom-up fill behavior. Current inventors note that others have proposed several theories to explain the bottom-filling behavior. One of the most successful theories is an additive accumulation theory proposed by Reid et al. See J. Reid, S. Mayer, E. Broadbent, E. Klawuhn and K. Ashtiani, “Factors influencing damascene feature fill using copper PVD and electroplating,” Solid State Technology, July, 2000. An illustration of additives behavior based on this theory is shown in FIGS. 4A-4G for a single trench and is described as follows: Once a wafer with a seed layer deposited is immersed in the plating solution (FIG. 4A), bath additives are adsorbed on the Cu seed surface, and an equilibrium level of additives is on all surfaces of the wafer, including both the side walls and the top and bottom of the trench (e.g. as shown in FIG. 4B at a time t=2 sec.). Due to the equilibrium level of chemical additives, once the current is applied on the solution bath, a conformal plating process will start first (t=10 sec., see FIG. 4C). After a certain amount of time (t=20 sec., see FIG. 4D), the accelerators, which can neither be incorporated into the deposited Cu surface, nor be desorbed into the plating solution, start to move to the bottom of the trench. The suppressors will be displaced by the accelerators due to their weaker adsorbing ability. This leads to a high concentration of accelerators on the bottom of the trench (t=30 sec, see FIG. 4E). Therefore the deposition rate on bottom is faster than on the sidewall and neck, making the deposition void free. The final surface may be planar (t=60 sec, see FIG. 4F) or have a bump (t=60 sec, see FIG. 4G) depending on the presence or absence of levelers and/or desorption of accelerators.
The above explanation, in paragraph [0010], of the super-fill mechanism has been proved to be successful and is adopted by several complicated numerical models, although not by Park. See T. P. Moffat, D. Wheeler, W. H. Huber and D. Josell, “Superconformal electrodeposition of copper,” Electrochemical and Solid-State Letters, Vol. 4, pp. C26-C29, 2001; D. Josell, D. Wheeler, W. H. Huber, J. E. Bonevich and T. P. Moffat, “A simple equation for predicting superconformal electrodeposition in submicrometer trenches,” Journal of the Electrochemical Society, Vol. 148, pp. C767-C773, 2001; and Y. H. Im, M. O. Bloomfield, S. Sen and T. S. Cale, “Modeling pattern density dependent bump formation in copper electrochemical deposition,” Electrochemical and Solid State Letters, Vol. 6, pp. C42-C46, 2003.
Current inventors have realized that one of the key ideas in the model described in paragraph [0010] is that there is no consumption of accelerators during ECP. The deposition rate increases with the amount of the accelerators in the trenches, which is determined by not only the area of the trench bottom but also by the area of the trench sidewall. For finer trenches with the same sidewall area, a faster deposition rate is expected due to a higher concentration of accelerators. Such an effect of accelerators is not taken into account by Park.